The invention relates generally to radio frequency (RF) power transistors and, more particularly, to circuits and methods for biasing such circuits.
The use of RF power transistor devices as signal amplifiers in wireless communication applications is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services, the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz frequencies. RF power transistors are commonly used in amplification stages for radio base station amplifiers. Such transistors are also widely used in other RF-related applications, such as cellular telephones, paging systems, navigation systems,-television, avionics, and military applications.
Existing wireless communications systems use modulation schemes that require the power amplifier to operate at peak power levels for extremely short duration. For example, in a third generation W-CDMA cellular system, the ratio of signal peak to average is about 8 dB (decibels), which means that the peak power delivered to the amplifier is about 8 dB higher than the average power delivered. The cumulative composite distribution function (CCDF) shows that the probability of occurrence of the peak amplitude of output signal is less than 0.01%.
The RF power transistors used to build these amplifiers are selected to be capable of handling the peak output power as the amplifier requires so they do not run into deep saturation and thereby cause highly non-linear distortion in the signal path when the peaks occur. Preferred transistors for such high frequency applications include laterally diffused metal oxide semiconductor (LDMOS) transistors. Notably, the transistors need to be operated in a low bias condition (i.e., class B and lower) for achieving the optimum drain efficiency, but in a high bias condition (i.e., closer to class A) for best linearity. Thus, power transistors used in RF amplifiers are typically biased under class AB condition, since that presents a trade-off between linearity and drain efficiency. However, this approach of choosing a transistor with a large gate periphery (greater peak power capability) to accommodate the occasional peaks in the modulating signal causes the amplifier system to be inefficient.
A previous solution to address this issue was the Doherty amplifier. A Doherty amplifier uses multiple amplifier circuits combined to achieve a high power system. These amplifiers are built with transistors that are biased differently to achieve higher efficiency in a power amplifier system. However, this causes difficulties in manufacturing due to banding of multiple packages. Additionally, the characteristics can be different for the individual transistors and hence can cause problems during power splitting and combining operations. Further, different matching elements need to be designed for each of the transistors, making the amplifier system bulky and cumbersome.
In accordance with a first embodiment of the invention, a power transistor circuit for use in a RF amplifier package comprises a single power transistor formed by a plurality of transistor elements, each transistor element having a separate input terminal. A resistor network is adapted for coupling the respective transistor element input terminals between a bias voltage and a reference ground. The resistor network includes a plurality of resistors located in a conductive xe2x80x9cbias pathxe2x80x9d coupling the bias voltage to the reference ground, with the individual transistor element inputs connected to the bias path at different locations. In particular, the resistive elements are interposed in the bias path between connection points of successive transistor element input terminals, such that the input terminals xe2x80x9cseexe2x80x9d a different dividing resistor network value due to the different cumulative resistance values at the respective connection points on the bias path. In one embodiment, the resistance values are selected such that a first transistor element is biased in a first (e.g., class A) operating condition, and a second transistor element is biased in a second (e.g., class AB) operating condition.
In one embodiment, first and second transistor elements of the power transistor are located on a single semiconductor substrate, and a resistive element connecting respective input terminals of the first and second transistor elements comprises a continuous resistive path disposed on the substrate.
In another embodiment, a first transistor element is located on a first semiconductor substrate, a second transistor element is located on a second semiconductor substrate, and a resistive element connecting respective input terminals of the first and second transistor elements comprises a conductor (e.g., a wire) extending between the first and second substrates.
In accordance with another aspect of the invention, a RF power package includes a single power transistor formed from a first set of one or more transistor elements located on a first die, the first set of transistor elements coupled to a first input terminal, and a second set of one or more transistor elements is located on a second die, the second set of transistor elements coupled to a second input terminal. A resistor network couples the first and second input terminals between a bias voltage terminal and a reference ground terminal. The resistor network includes a plurality of resistors located along a conductive bias path coupling the bias voltage terminal to the reference ground terminal, with the first and second input terminals connected to the bias path at different locations. Respective resistive elements interposed along the bias path between the connection points of the first and second input terminals are sized such that the first set of transistor elements is biased in a first (e.g., class A) operating condition, and the second set of transistor elements is biased in a second (e.g., class AB) operating condition.
In accordance with still another aspect of the invention, a method of biasing a power transistor is provided, the power transistor comprising a plurality of transistor elements. In one embodiment, the method includes biasing a first transistor element in a first (e.g., class A) operating condition, and biasing a second transistor element in a second (e.g., class AB) operating condition.
Other aspects and features of the present invention will become apparent from consideration of the following description taken in conjunction with the accompanying drawings.